Memory devices are used to store data. The demand for large memory systems with high bandwidth has increased during recent years. For large memory systems, several devices may share a common bus. For example, the data bus or the clock signal may share a single bus, or a set of conductive elements. This bus sharing causes an increase in the capacitive loading of each device. The increased loading degrades signal quality as well as the switching speed of signals, which then requires slower clocking and consequently reduced bandwidth.
A daisy-chained interconnection 100, is shown in FIG. 1, and a loop chained interconnection 200 is shown in FIG. 2, wherein memory devices are connected in series to reduce capacitive loading on the bus. However each memory device does not use the full channel but rather just half of the channel to write or read data because data flows only in one direction when the write command or the read command issues.